Analysis of Coprocessor-based Acceleration for Hardware-based Semaphore Concurrency Control

Authors

  • Michal Walichiewicz Silesian University of Technology, Poland
  • Adam Milik Silesian University of Technology, Poland

DOI:

https://doi.org/10.24425/ijet.2026.1733

Abstract

Coprocessors are widely integrated into modern microprocessors, particularly in safety-critical systems. They handle interrupts and accelerate computationally intensive operations, such as cryptographic and floating-point calculations; furthermore, they enable separation between system components. This article adopts a structured approach to provide a formal description of coprocessors and their role within modern microprocessor architectures. In addition, a concurrency control system based on Inter-Processor Interrupts (IPIs) is presented and compared with a polling-based synchronization approach using hardware-based semaphores. Finally, this study evaluates whether coprocessors can be utilized to accelerate multi-core synchronization by executing computations in parallel with synchronization.

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Published

2026-07-31

How to Cite

Walichiewicz, Michal, and Adam Milik. “Analysis of Coprocessor-Based Acceleration for Hardware-Based Semaphore Concurrency Control”. International Journal of Electronics and Telecommunications, vol. 72, no. 3, July 2026, pp. 1-11, doi:10.24425/ijet.2026.1733.

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Artykuły