B, Neeraja; K, Vasanth; SREE B, Bhavya; SREE M, Jaya; VARSHINI G, Deekshitha; E, Chandrasekhar; T, Nagalaxmi. Design and analysis of PTL based reversible logic encoder circuits for low-power applications. International Journal of Electronics and Telecommunications, [S. l.], v. 72, n. 2, 2026. DOI: 10.24425/ijet.2026.157936 ©. Disponível em: https://wydawnictwo.pan.pl/index.php/ijet/article/view/1126. Acesso em: 6 jun. 2026.