KOPCZYNSKI , Maciej. Scalable FPGA Hardware Architecture for Parallel Reduct Computation in Big Datasets Using Rough Sets . International Journal of Electronics and Telecommunications, [S. l.], v. 72, n. 3, p. 1–7, 2026. DOI: 10.24425/ijet.2026.1721. Disponível em: https://wydawnictwo.pan.pl/index.php/ijet/article/view/1721. Acesso em: 1 sep. 2026.