Performance analysis of RISC-V based cores in a dual-core programmable logic controller

Abstract

The article presents the concept of dual-core bit.WORD programmable logic controller central processing unit. The idea is based on the use of two microprocessor cores, one fast and low-power for bit operations and one computationally efficient for word operations. The main contribution is a comparison of efficiency of the bit core and the word core. The paper presents results for logic utilization, core clock frequency and power consumption in order to undertake further implementation work related to the development of the bit.WORD unit.