Low-power logic function implementation by means of SOP networks

Abstract

Energy-efficient implementation of digital circuits is a key development direction in modern electronics, especially in the context of the growing demand for mobile and integrated computing systems. Reducing energy consumption not only extends battery life but also reduces heat emission, simplifying the design of cooling systems and increasing system reliability. This article presents a method for designing energy-efficient combinational circuits implemented as SOP networks. The essence of the solution is to modify the classical method known from the literature to minimize the number of switching events across the entire network, taking into account varying switching probabilities of input signals. Unlike previous works, which assumed identical switching probabilities, the proposed approach takes into account their actual, varying distributions. Additionally, the number of logic levels is taken into account. The main goal of the method is to reduce the switching activity of the SOP network, thus reducing dynamic power consumption. The proposed solution is universal: it allows for the search for energy-efficient configurations regardless of the implementation technology, focusing solely on limiting the number of switching events in the implemented system. The developed algorithm for technology mapping logic functions into energyefficient SOP networks has been verified using numerous benchmarks. Experimental results confirm its high efficiency and significant potential for dynamic power reduction.