Fast data transmission with FPGAs for implementation in ALICE FIT detector in CERN

Abstract

In high-energy physics experiments, massive amounts of data need to be processed. The limitations of peripherals in field-programmable gate arrays (FPGAs), such as analog-to-digital converters (ADCs), make it impractical to design setups based solely on a single FPGA chip, creating a need for high-speed, low-latency methods for inter-chip data transmission, where multi-gigabit transceivers (MGTs) are essential. This paper aims to assess the feasibility of using MGTs in the readout electronics of the fast interaction trigger (FIT) detector within the A Large Ion Collider Experiment (ALICE) at CERN. It examines two established protocols, i.e. Aurora 8b/10b and Aurora 64b/66b, focusing on their throughput and latency. Additionally, it presents a custom protocol based on 64b/66b encoding, specifically designed to reduce latency, and compares its performance with standard solutions. Transmission tests were conducted between two Xilinx boards, ZCU102 and ZCU106, using both the Aurora protocols and the custom protocol. Furthermore, transmission quality was evaluated based on the type and length of the transmission medium as well as on the lengths of the pseudo-random binary sequence (PRBS).