Designing safe finite state machines

Abstrakt

This paper addresses the design of safe finite state
machines (SFSMs) using the Verilog hardware description
language (HDL) alongside the Quartus design tool to implement
FSMs on field-programmable gate arrays (FPGAs). Three styles
of finite state machine (FSM) description are proposed (safe,
safe_error, and safe_idle), which provide different options for
SFSM implementation. Experimental studies on FSM
benchmarks have shown that the presented approach reduces
SFSM area by an average factor of 2.436 and improves
performance by an average factor of 1.588 compared to
synthesizing SFSMs in the Quartus design tool.
Recommendations are also provided on the practical application
of this approach for designing SFSMs.