The impact of digital delay lines’ spatial allocation on the DPS synchronization quality
DOI:
https://doi.org/10.24425/mms.2025.154677Abstract
The paper concerns the optimization methodology of design of a high-resolution digital phase synchronizer (DPS) module cooperating with a multi-channel coincidence counter. The main function of the DPS module was to ensure high synchronization between the measurement system and trigger pulses (with various repetition rates) from the photo detector. With this approach, it became possible to adapt the measurement system to work with a wide spectrum of excitation sources while maintaining the required metrological parameters. The DPS resolution is determined by the architecture of coding tapped delay lines (TDLs) utilized, whereas the degree of synchronization is determined by the differences in their integral nonlinearity errors (Δ𝑅INL). In traditional DPS designs, the basis for synchronization were single TDLs built on arithmetic carry chain paths, which are usually characterized by high nonlinearity. The approach presented in this paper assumes the use of complex tapped delay lines (CTDLs) and an appropriate selection of spatial TDLs allocations within a programmable logic structure. The proposed solution enables an effective minimization (from 62.6 ps to 26.2 ps) of the synchronization error between the measurement system and the investigated process.References
[1] Kalisz, J., Szplet, R., Pasierbinski, J., & Poniecki, A. (1997). Field-programmable-gate-array-based time-to-digital converter with 200-ps resolution. IEEE Transactions on Instrumentation and Measurement, 46(1), 51-55. https://doi.org/10.1109/19.552156
[2] Zieliński, M., Chaberski, D., Kowalski, M., Frankowski, R., & Grzelak, S. (2004). High-resolution time-interval measuring system implemented in single FPGA device. Measurement, 35(3), 311-317. https://doi.org/10.1016/j.measurement.2003.12.001
[3] Wu, J., & Shi, Z. (2008). The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay. IEEE Nuclear Science Symposium Conference Record. https://doi.org/10.1109/nssmic.2008.4775079
[4] Chen, N. Y. (2013). A high resolution FPGA-based merged delay line TDC with nonlinearity calibration. 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2432-2435. https://doi.org/10.1109/iscas.2013.6572370
[5] Machado, R., Cabral, J., & Alves, F. S. (2019). Recent developments and challenges in FPGA-Based Time-to-Digital Converters. IEEE Transactions on Instrumentation and Measurement, 68(11), 4205-4221. https://doi.org/10.1109/tim.2019.2938436
[6] Kwiatkowski, P. (2019). Employing FPGA DSP blocks for time-to-digital conversion. Metrology and Measurement Systems, 26(4), 631-643. https://doi.org/10.24425/mms.2019.130570
[7] Sondej, D., Szymanowski, R., & Szplet, R. (2021). Methods of precise determining the transfer function of picosecond time-to-digital converters. Metrology and Measurement Systems, 28(3), 539-549. https://doi.org/10.24425/mms.2021.137697
[8] Xie, W., Chen, H., & Li, D. D. (2021). Efficient Time-to-Digital Converters in 20 nm FPGAs with Wave Union Methods. IEEE Transactions on Industrial Electronics, 69(1), 1021-1031. https://doi.org/10.1109/tie.2021.3053905
[9] Kwiatkowski, P., Sondej, D., & Szplet, R. (2023). Subpicosecond resolution time interval counter with multisampling wave union type B TDCs in 28 nm FPGA device. Measurement, 209, 112510. https://doi.org/10.1016/j.measurement.2023.112510
[10] Szplet, R., Jachna, Z., Kwiatkowski, P., & Rozyc, K. (2013). A 2.9 ps equivalent resolution interpolating time counter based on multiple independent coding lines. Measurement Science and Technology, 24(3), 035904. https://doi.org/10.1088/0957-0233/24/3/035904
[11] Chaberski, D., Frankowski, R., Zieliński, M., & Zaworski, Ł. (2016). Multiple-tapped-delay-line hardware-linearisation technique based on wire load regulation. Measurement, 92, 103-113. 10.1016/j.measurement.2016.06.002
[12] Frankowski, R., Gurski, M., & Płóciennik, P. (2016). Optical methods of the delay cells characteristics measurements and their applications. Optical and Quantum Electronics, 48(3). https://doi.org/10.1007/s11082-016-0465-6
[13] Chaberski, D., Frankowski, R., Gurski, M., & Zieliński, M. (2017). Comparison of interpolators used for time-interval measurement systems based on multiple-tapped delay line. Metrology and Measurement Systems, 24(2), 401-412. http://dx.doi.org/10.1515/mms-2017-0033
[14] Wang, Y., Cao, Q., & Liu, C. (2017). A multi-chain merged tapped delay line for high precision time-to-digital converters in FPGAs. IEEE Transactions on Circuits & Systems II Express Briefs, 65(1), 96-100. https://doi.org/10.1109/tcsii.2017.2698479
[15] Frankowski, R., Gurski, M., & Szplet, R. (2024). Kintex UltraScale’s multi-segment digital tapped delay lines with controlled characteristics for precise time-to-digital conversion. Metrology and Measurement Systems, 31(2), 417-429. https://doi.org/10.24425/mms.2024.149697
[16] Frankowski, R., Chaberski, D., Kowalski, M., & Zieliński, M. (2017). A high-speed fully digital phase-synchronizer implemented in a field programmable gate array device. Metrology and Measurement Systems, 24(3), 537-550. https://doi.org/10.1515/mms-2017-0037
[17] Kwiatkowski, P., & Szplet, R. (2020). Efficient implementation of multiple time coding lines-based TDC in an FPGA device. IEEE Transactions on Instrumentation and Measurement, 69(10), 7353-7364. https://doi.org/10.1109/tim.2020.2984929
[18] Morabito, M., Lusardi, N., Garzetti, F., Fiumicelli, G., Bonanno, G., Ronconi, E., Costa, A., & Geraci, A. (2024). Optimal Implementation of Tapped Delay Line Time-to-Digital Converters in 20 nm Xilinx UltraScale FPGAs. Electronics, 13(24), 4888. https://doi.org/10.3390/electronics13244888
[19] Rahman, M., Baishnab, K. L., & Talukdar, F. A. (2010, February). A novel ROM architecture for reducing bubble and metastability errors in high speed flash ADCs. In 2010 20th International Conference on Electronics Communications and Computers (CONIELECOMP), 15-19. https://doi.org/10.1109/conielecomp.2010.5440805
[20] Gurski, M., Frankowski, R., & Zieliński, M. (2021). Algorytmy minimalizacji błędu bąbelkowego w precyzyjnej metrologii odcinka czasu. Przegląd Elektrotechniczny, 1(10), 102-104. (in Polish). https://doi.org/10.15199/48.2021.10.20
[21] Wu, J. (2010). Several key issues on implementing delay line based TDCs using FPGAs. IEEE Transactions on Nuclear Science, 57(3), 1543-1548. https://doi.org/10.1109/tns.2010.2045901
[22] Cova, S., & Bertolaccini, M. (1970). Differential linearity testing and precision calibration of multichannel time sorters. Nuclear Instruments and Methods, 77(2), 269-276. https://doi.org/10.1016/0029-554x(70)90095-9