High-precision 3-channel time interval counter in a low-cost AMD Spartan-7 FPGA

Authors

  • Ryszard Szplet Military University of Technology, Faculty of Electronics, Institute of Telecommunication, ul gen. Sylwestra Kaliskiego 2, 00-908 Warsaw, Poland
  • Paweł Kwiatkowski Military University of Technology, Faculty of Electronics, Institute of Telecommunication, ul gen. Sylwestra Kaliskiego 2, 00-908 Warsaw, Poland
  • Krzysztof Różyc Military University of Technology, Faculty of Electronics, Institute of Telecommunication, ul gen. Sylwestra Kaliskiego 2, 00-908 Warsaw, Poland
  • Dominik Sondej Military University of Technology, Faculty of Electronics, Institute of Telecommunication, ul gen. Sylwestra Kaliskiego 2, 00-908 Warsaw, Poland
  • Zbigniew Jachna Military University of Technology, Faculty of Electronics, Institute of Telecommunication, ul gen. Sylwestra Kaliskiego 2, 00-908 Warsaw, Poland
  • Jakub Tyburski Military University of Technology, Faculty of Electronics, Institute of Telecommunication, ul gen. Sylwestra Kaliskiego 2, 00-908 Warsaw, Poland
  • Paweł Ślązak Military University of Technology, Faculty of Electronics, Institute of Telecommunication, ul gen. Sylwestra Kaliskiego 2, 00-908 Warsaw, Poland
  • Albin Czubla Division of Time and Length, Central Office of Measures, ul. Elektoralna 2, 00-139 Warsaw, Poland
  • Piotr Szterk Division of Time and Length, Central Office of Measures, ul. Elektoralna 2, 00-139 Warsaw, Poland

DOI:

https://doi.org/10.24425/mms.2025.155804

Keywords

time interval measurement, time interval counter, time-to-digital converter, TDC, field-programmable gate array, FPGA

Abstract

This paper presents the design, implementation, and performance evaluation of a 3-channel integrated time interval counter implemented in a low-cost Spartan-7 (AMD/Xilinx) FPGA device. Based on a hybrid measurement approach that combines timestamping and two-stage interpolation, the proposed solution provides high metrological parameters, such as: time resolution (2 ps), measurement precision (better than 8 ps) and range (up to 1 h). To achieve high resolution and reduce nonlinearity of the time-to-digital converters (TDCs) involved, the multi-edge coding in four independent tapped delay lines (TDL) was applied. An improved encoder eliminates bubble errors and compresses raw TDL data with limited logic overhead. The integrated code processor performs real-time calibration based on the statistical code density test (SCDT). Implemented within a low-end FPGA chip, the time counter occupies approximately one-third of available logic resources and consumes around 0.5 W. Experimental evaluation confirms the system’s potential for cost-effective, high-performance time interval measurements in portable instrumentation.

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Published

2025-09-30

How to Cite

Szplet, Ryszard, et al. “High-Precision 3-Channel Time Interval Counter in a Low-Cost AMD Spartan-7 FPGA”. Metrology and Measurement Systems, vol. 32, no. 3, Sept. 2025, pp. art. no. 14, 1-15, doi:10.24425/mms.2025.155804.

Issue

Vol. 32 No. 3 (2025)

Section

Articles